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LTC1272 12-Bit, 3s, 250kHz Sampling A/D Converter
FEATURES
s s s s s s s s s s s
DESCRIPTIO
AD7572 Pinout 12-Bit Resolution 3s and 8s Conversion Times On-Chip Sample-and-Hold Up to 250kHz Sample Rates 5V Single Supply Operation No Negative Supply Required On-Chip 25ppm/C Reference 75mW (Typ) Power Consumption 24-Pin Narrow DIP and SOL Packages ESD Protected on All Pins
The LTC1272 is a 3s, 12-bit, successive approximation sampling A/D converter. It has the same pinout as the industry standard AD7572 and offers faster conversion time, on-chip sample-and-hold, and single supply operation. It uses LTBiCMOSTM switched-capacitor technology to combine a high speed 12-bit ADC with a fast, accurate sample-and-hold and a precision reference. The LTC1272 operates with a single 5V supply but can also accept the 5V/-15V supplies required by the AD7572 (Pin 23, the negative supply pin of the AD7572, is not connected on the LTC1272). The LTC1272 has the same 0V to 5V input range as the AD7572 but, to achieve single supply operation, it provides a 2.42V reference output instead of the - 5.25V of the AD7572. It plugs in for the AD7572 if the reference capacitor polarity is reversed and a 1s sampleand-hold acquisition time is allowed between conversions. The output data can be read as a 12-bit word or as two 8-bit bytes. This allows easy interface to both 8-bit and higher processors. The LTC1272 can be used with a crystal or an external clock and comes in speed grades of 3s and 8s.
LTBiCMOS is a trademark of Linear Technology Corporation
APPLICATI
s s s s
S
High Speed Data Acquisition Digital Signal Processing (DSP) Multiplexed Data Acquisition Systems Single Supply Systems
TYPICAL APPLICATI
2.42V VREF OUTPUT ANALOG INPUT (0V TO 5V) A IN VREF 10F AGND
Single 5V Supply, 3s, 12-Bit Sampling ADC
LTC1272 VDD NC BUSY CS RD HBEN CLK OUT CLK IN D0/8 D1/9 D2/10 D3/11
-120 -140 0
1024 Point FFT, fS = 250kHz, fIN = 10kHz
5V
0
+
0.1F
10 F
+
-20
0.1 F
-40
AMPLITUDE (dB)
D11 (MSB) D10 D9 D8 D7 8 OR 12-BIT PARALLEL BUS D6 D5 D4 DGND
P CONTROL LINES
-60 -80 -100
20
LTC1272 * TA01
U
S = 72.1 (N+D) 40 60 80 100 120
LTC1272 * TA02
UO
UO
FREQUENCY (kHz)
1
LTC1272 ABSOLUTE
(Notes 1 and 2)
AXI U
RATI GS
Operating Temperature Range LTC1272-XAC, CC ................................. 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
Supply Voltage (VDD) ................................................. 6V Analog Input Voltage (Note 3) ................... - 0.3V to 15V Digital Input Voltage .................................. - 0.3V to 12V Digital Output Voltage .................... - 0.3V to VDD + 0.3V Power Dissipation .............................................. 500mW
PACKAGE/ORDER I FOR ATIO
TOP VIEW A IN VREF AGND (MSB) D11 D10 D9 D8 D7 D6 1 2 3 4 5 6 7 8 9 24 VDD 23 NC 22 BUSY 21 CS 20 RD 19 HBEN 18 CLK OUT 17 CLK IN 16 D0/8 15 D1/9 14 D2/10 13 D3/11 A IN VREF AGND (MSB) D11 D10 D9 D8 D7 D6 1 2 3 4 5 6 7 8 9
TOP VIEW 24 VDD 23 NC 22 BUSY 21 CS 20 RD 19 HBEN 18 CLK OUT 17 CLK IN 16 D0/8 15 D1/9 14 D2/10 13 D3/11 S PACKAGE 24-LEAD PLASTIC SOL
D5 10 D4 11 DGND 12
D5 10 D4 11 DGND 12
N PACKAGE 24-LEAD PLASTIC DIP
TJMAX = 110C, JA = 100C/W
TJMAX = 110C, JA = 130C/W
Consult factory for Industrial and Military grade parts.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error (Note 5) CONDITIONS
Gain Error Full-Scale Tempco IOUT (Reference) = 0
q
2
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WW
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ORDER PART NUMBER CONVERSION TIME = 3s LTC1272-3ACN LTC1272-3CCN CONVERSION TIME = 8s LTC1272-8ACN LTC1272-8CCN
S PACKAGE ONLY LTC1272-3ACS LTC1272-3CCS LTC1272-8ACS LTC1272-8CCS
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With Internal Reference (Note 4)
LTC1272-XA MIN
q q q q
LTC1272-XC MAX 1/2 1 3 4 10 MIN 12 1 1 4 6 15 10 45 TYP MAX UNITS Bits LSB LSB LSB LSB LSB ppm/C
TYP
12
5
25
LTC1272
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage (Note 6) VREF Output Tempco VREF Line Regulation CONDITIONS IOUT = 0 IOUT = 0 4.75V VDD 5.25V, IOUT = 0
q
VREF Load Regulation (Sourcing Current) 0 OUT 1mA I
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
SYMBOL VIH VIL IIN VOH VOL IOZ COZ ISOURCE ISINK IDD PD PARAMETER High Level Input Voltage CS, RD, HBEN, CLK IN Low Level Input Voltage CS, RD, HBEN, CLK IN Input Current CS, RD, HBEN Input Current CLK IN High Level Output Voltage All Logic Outputs Low Level Output Voltage All Logic Outputs High-Z Output Leakage D11-D0/8 High-Z Output Capacitance (Note 7) Output Source Current Output Sink Current Positive Supply Current Power Dissipation VOUT = 0V VOUT = VDD CS = RD = VDD, AIN = 5V CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD VIN = 0V to VDD VDD = 4.75V IOUT = - 10A IOUT = - 200A VDD = 4.75V, IOUT = 1.6mA VOUT = 0V to VDD
DY A IC ACCURACY
SYMBOL S/(N + D) THD PARAMETER
Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion (Up to 5th Harmonic) Peak Harmonic or Spurious Noise
A ALOG I PUT
SYMBOL VIN IIN CIN tACQ PARAMETER Input Voltage Range Input Current Input Capacitance
Sample-and-Hold Acquisition Time
U
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WU
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(Note 4)
LTC1272-XA TYP MAX 2.420 5 0.01 2 2.440 25 MIN 2.400 LTC1272-XC TYP MAX 2.420 10 0.01 2 2.440 45 UNITS V ppm/C LSB/V LSB/mA
MIN 2.400
(Note 4)
LTC1272-XA/C MIN TYP MAX
q q q q
UNITS V V A A V V
2.4 0.8 10 20 4.7 4.0 0.4 10 15 - 10 10
q q q q
V A pF mA mA
q
15 75
30
mA mW
(Note 4) fSAMPLE = 250kHz (LTC1272-3), 111kHz (LTC1272-8)
CONDITIONS 10kHz Input Signal 10kHz Input Signal 10kHz Input Signal MIN LTC1272-XA/C TYP MAX 72 - 82 - 82 UNITS dB dB dB
(Note 4)
CONDITIONS 4.75V VDD 5.25V
q q
MIN 0
LTC1272-XA/B/C TYP MAX 5 3.5 50 0.45 1
UNITS V mA pF s
q
3
LTC1272
TI I G CHARACTERISTICS
SYMBOL t1 t2 t3 PARAMETER CS to RD Setup Time RD to BUSY Delay Data Access Time After RD
t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 tCONV
The q indicates specifications which apply over the full operating temperature range; all other limits and typicals TA = 25C. Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together, unless otherwise noted. Note 3: When the analog input voltage is taken below ground it will be clamped by an internal diode. This product can handle, with no external diode, input currents of greater than 60mA below ground without latch-up. Note 4: VDD = 5V, fCLK = 4MHz for LTC1272-3, and 1.6MHz for LTC1272-8, t r = t f = 5ns unless otherwise specified. For best analog performance, the LTC1272 clock should be synchronized to the RD and CS control inputs with at least 40ns separating convert start from the nearest clock edge.
4
UW
(Note 8)
CONDITIONS
q
LTC1272-XA/C MIN TYP MAX 0 80
q
UNITS ns ns ns ns ns ns ns ns ns ns
CL = 50pF COM Grade CL = 20pF COM Grade CL = 100pF COM Grade
190 230 90 110 125 150
50
q
70
q q q
RD Pulse Width COM Grade CS to RD Hold Time Data Setup Time After BUSY COM Grade Bus Relinquish Time COM Grade HBEN to RD Setup Time HBEN to RD Hold Time Delay Between RD Operations Delay Between Conversions Aperture Delay of Sample and Hold CLK to BUSY Delay COM Grade Conversion Time
q q q q q q q
t3 t3 0 40 20 20 0 0 200 1 25 80 12 170 220 13 30 70 90 75 85
ns ns ns ns ns ns ns s ns ns ns CLK CYCLES
Jitter < 50ps
Note 5: Linearity error is specified between the actual end points of the A/D transfer curve. Note 6: The LTC1272 has the same 0V to 5V input range as the AD7572 but, to achieve single supply operation, it provides a 2.42V reference output instead of the -5.25V of the AD7572. This requires that the polarity of the reference bypass capacitor be reversed when plugging an LTC1272 into an AD7572 socket. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 5V. Timing specifications are sample tested at 25C to ensure compliance. All input control signals are specified with tr = tf = 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. See Figures 13 through 17.
LTC1272
PI FU CTI UO
D11 DB11 DB11
AIN (Pin 1): Analog Input, 0V to 5V Unipolar Input. VREF (Pin 2): 2.42V Reference Output. When plugging into an AD7572 socket, reverse the reference bypass capacitor polarity and short the 10 series resistor. AGND (Pin 3): Analog Ground. D11 to D4 (Pins 4-11): Three-State Data Outputs. DGND (Pin 12): Digital Ground. D3/11 to D0/8 (Pins 13-16): Three-State Data Outputs. CLK IN (Pin 17): Clock Input. An external TTL/CMOS compatible clock may be applied to this pin or a crystal can be connected between CLK IN and CLK OUT. CLK OUT (Pin 18): Clock Output. An inverted CLK IN signal appears at this pin.
Data Bus Output, CS and RD = LOW
Pin 4 MNEMONIC* HBEN = LOW HBEN = HIGH Pin 5 D10 DB10 DB10 Pin 6 D9 DB9 DB9 Pin 7 D8 DB8 DB8 Pin 8 D7 DB7 LOW
*D11...D0/8 are the ADC data output pins. DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity
1.0 VDD = 5V fCLK = 4MHz 0.5
INL ERROR (LSBs)
UW
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S
HBEN (Pin 19): High Byte Enable Input. This pin is used to multiplex the internal 12-bit conversion result into the lower bit outputs (D7 to D0/8). See table below. HBEN also disables conversion starts when HIGH. RD (Pin 20): Read Input. This active low signal starts a conversion when CS and HBEN are low. RD also enables the output drivers when CS is low. CS (Pin 21): The Chip Select Input must be low for the ADC to recognize RD and HBEN inputs. BUSY (Pin 22): The BUSY Output is low when a conversion is in progress. NC (Pin 23): Not Connected Internally. The LTC1272 does not require negative supply. This pin can accommodate the -15V required by the AD7572 without problems. VDD (Pin 24): Positive Supply, 5V.
Pin 9 D6 DB6 LOW
Pin 10 D5 DB5 LOW
Pin 11 D4 DB4 LOW
Pin 13 D3/11 DB3 DB11
Pin 14 D2/10 DB2 DB10
Pin 15 D1/9 DB1 DB9
Pin 16 D0/8 DB0 DB8
0
- 0.5
-1.0 0 512 1024 1536 2048 CODE
LTC1272 * TPC01
2560
3072
3584
4096
5
LTC1272
TYPICAL PERFOR A CE CHARACTERISTICS
Differential Nonlinearity
1.0 VDD = 5V fCLK = 4MHz 0.5
INL ERROR (LSBs)
VDD Supply Current vs Temperature
30
600
VDD SUPPLY CURRENT, IDD (mA)
25 20 15 10 5
VDD = 5V fCLK = 4MHz
CLOCK FREQUENCY (kHz)
CLOCK FREQUENCY (MHz)
0 - 55 -25
0
25
50
75
TEMPERATURE (C)
LT1272 * TPC03
VREF vs ILOAD (mA)
2.435 2.430 2.425 VREF (V) 2.420 2.415 2.410 2.405 -5 -4 -3 -2 -1 0 1 2 IL (mA)
LT1272 * TPC06
ENOBs*
6
UW
100
0
-0.5
-1.0 0 512 1024 1536 2048 CODE
LTC1272 * TPC02
2560
3072
3584
4096
Minimum Clock Frequency vs Temperature
8
VDD = 5V 500 400 300 200 100 0 - 55 -25
Maximum Clock Frequency vs Temperature
7 6 5 4 3 2 -55 -25
125
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (C)
LT1272 * TPC04
TEMPERATURE (C)
LT1272 * TPC05
LTC1272 ENOBs* vs Frequency
12 11 10 9 8 7 6 5 4 3 2 1 0 0 20 40 60 80 100 120 fIN (kHz)
LT1272 * TPC07
fS = 250kHz VDD = 5V
S/(N + D) - 1.76dB *EFFECTIVE NUMBER OF BITS, ENOBs = 6.02
LTC1272
APPLICATI
S I FOR ATIO
Conversion Details Conversion start is controlled by the CS, RD and HBEN inputs. At the start of conversion the successive approximation register (SAR) is reset and the three-state data outputs are enabled. Once a conversion cycle has begun it cannot be restarted. During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN input connects to the sample-and-hold capacitor through a 300/2.7k divider. The voltage divider allows the LTC1272 to convert 0V to 5V input signals while operating from a 4.5V supply. The conversion has two phases: the sample phase and the convert phase. During the sample phase, the comparator offset is nulled by the feedback switch and the analog input is stored as a charge on the sample-and-hold capacitor, CSAMPLE. This phase lasts from the end of the previous conversion until the next conversion is started. A minimum delay between conversions (t10) of 1s allows enough time for the analog input to be acquired. During the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. The sample-and-hold capacitor is switched to ground injecting the analog input charge onto the comparator summing junction. This input charge is successively compared to binary weighted charges supplied by the capacitive DAC. Bit decisions are made by the comparator (zero crossing detector) which checks the addition of each successive weighted bit from the DAC output. The MSB decision is made 50ns (typically) after the second falling edge of CLK IN following a conversion start. Similarly, the succeeding bit decisions are made approximately 50ns after a CLK IN edge until the conversion is finished. At the end of a conversion, the DAC output balances the AIN output charge. The SAR contents (12-bit data word) which represent the AIN input signal are loaded into a 12-bit latch. Sample-and-Hold and Dynamic Performance Traditionally A/D converters have been characterized by such specs as offset and full-scale errors, integral
AMPLITUDE (dB)
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AIN SAMPLE 300 SAMPLE HOLD 2.7k CDAC DAC VDAC S A R CSAMPLE SI
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- +
COMPARATOR
12-BIT LATCH
LTC1272 * TA07
Figure 1. AIN Input
nonlinearity and differential nonlinearity. These specs are useful for characterizing an ADC's DC or low frequency signal performance. These specs alone are not adequate to fully specify the LTC1272 because of its high speed sampling ability. FFT (Fast Fourrier Transform) test techniques are used to characterize the LTC1272's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using a FFT algorithm, the LTC1272's spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1272 FFT plot.
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0 20 40 60 80 100 120 FREQUENCY (kHz)
LTC1272 * TA23
Figure 2. LTC1272 Non-Averaged, 1024 Point FFT Plot. fS = 250kHz, fIN = 10kHz
7
LTC1272
APPLICATI S I FOR ATIO U
1.0 0.5 ERROR (LSB) 0 -0.5 -1.0 0 1 2 CODE (THOUSANDS) 3 4
LTC1272 * TA24
Signal-to-Noise Ratio The Signal-to-Noise Ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. This includes distortion as well as noise products and for this reason it is sometimes referred to as Signal-to-Noise + Distortion [S/(N + D)]. The output is band limited to frequencies from DC to one half the sampling frequency. Figure 2 shows spectral content from DC to 125kHz which is 1/2 the 250kHz sampling rate. Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an A/D and is directly related to the S/(N + D) by the equation: N = [S/(N + D) -1.76]/6.02, where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 250kHz the LTC1272 maintains 11.5 ENOBs or better to 20kHz. Above 20kHz the ENOBs gradually decline, as shown in Figure 3, due to increasing second harmonic distortion. The noise floor remains approximately 90dB. The dynamic differential nonlinearity remains good out to 120kHz as shown in Figure 4.
12 11 10 9 8 7 6 5 4 3 2 1 0 0 20 40 60 80 100 120 fIN (kHz)
LT1272 * TPC07
ENOBs*
fS = 250kHz VDD = 5V
S/(N D) 1 76dB
Figure 3. LTC1272 Effective Number of Bits (ENOBs) vs Input Frequency. fS = 250kHz
8
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Figure 4. LTC1272 Dynamic DNL. fCLK = 4MHz, fS = 250kHz, fIN = 122.25342kHz, VCC = 5V
Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The harmonics are limited to the frequency band between DC and one half the sampling frequency. THD is expressed as: 20 LOG [V22 + V32 + ... + VN2 / V1] where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. Clock and Control Synchronization For best analog performance, the LTC1272 clock should be synchronized to the CS and RD control inputs as shown in Figure 5, with at least 40ns separating convert start from the nearest CLK IN edge. This ensures that transitions at CLK IN and CLK OUT do not couple to the analog input and get sampled by the sample-and-hold. The magnitude of this feedthrough is only a few millivolts, but if CLK and convert start (CS and RD) are asynchronous, frequency components caused by mixing the clock and convert signals may increase the apparent input noise. When the clock and convert signals are synchronized, small endpoint errors (offset and full-scale) are the most that can be generated by clock feedthrough. Even these errors (which can be trimmed out) can be eliminated by ensuring that the start of a conversion (CS and RD's falling edge) does not occur within 40ns of a clock edge, as in
LTC1272 APPLICATI S I FOR ATIO
CS & RD t2 BUSY 40ns* CLK IN t14 DB11 (MSB) DB10 DB1 DB0 (LSB) t13
UNCERTAIN CONVERSION TIME FOR 30ns < t14 < 180ns *THE LTC1272 IS ALSO COMPATIBLE WITH THE AD7572 SYNCHRONIZATION MODES.
LTC1272 * TA06
Figure 5. RD and CLK IN for Synchronous Operation
Figure 5. Nevertheless, even without observing this guideline, the LTC1272 is still compatible with AD7572 synchronization modes, with no increase in linearity error. This means that either the falling or rising edge of CLK IN may be near RD's falling edge. Driving the Analog Input The analog input of the LTC1272 is much easier to drive than that of the AD7572. The input current is not modulated by the DAC as in the AD7572. It has only one small current spike from charging the sample-and-hold capacitor at the end of the conversion. During the conversion the analog input draws only DC current. The only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion is started. Any op amp that settles in 1s to small current transients will allow maximum speed operation. If slower op amps are used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the LTC1272 AIN input include the LT1006 and LT1007 op amps. Internal Clock Oscillator Figure 6 shows the LTC1272 internal clock circuit. A crystal or ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18) to provide a clock oscillator for ADC timing. Alternatively the crystal/resonator may be omitted and an external clock source may be
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t CONV
C1 C2 CLK OUT 18 17 CLK IN 1M CLOCK LTC1272 NOTES: LTC1272-3 - 4MHz CRYSTAL/CERAMIC RESONATOR LTC1272-8 - 1.6MHz CRYSTAL/CERAMIC RESONATOR
LTC1272 * TA09
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Figure 6. LTC1272 Internal Clock Circuit
connected to CLK IN. For an external clock the duty cycle is not critical. An inverted CLK IN signal will appear at the CLK OUT pin as shown in the operating waveforms of Figure 7. Capacitance on the CLK OUT pin should be minimized for best analog performance. Internal Reference The LTC1272 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.42V 1%. It is internally connected to the DAC and is also available at pin 2 to provide up to 1mA current to an external load. For minimum code transition noise the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10F tantalum in parallel with a 0.1F ceramic). A simplified schematic of the reference with its recommended decoupling is shown in Figure 8.
9
LTC1272
APPLICATI S I FOR ATIO
CS & RD
BUSY 50ns TYP CLK IN
CLK OUT
Figure 7. Operating Waveforms Using an External Clock Source for CLK IN
5V CURVATURE CORRECTED BANDGAP REFERENCE
LTC1272
+ -
OUTPUT CODE
TO DAC
AGND 3 0.1F 2
VREF
10 F
LTC1272 * TA10
Figure 8. LTC1272 Internal 2.42V Reference
Unipolar Operation Figure 9 shows the ideal input/output characteristic for the 0V to 5V input range of the LTC1272. The code transitions occur midway between successive integer LSB values (i.e., 1/2LSB, 3/2LSBs, 5/2LSBs . . . FS - 3/2LSBs). The output code is natural binary with 1 LSB = FS/4096 = (5/4096)V = 1.22mV. Unipolar Offset and Full-Scale Error Adjustment In applications where absolute accuracy is important, then offset and full-scale error can be adjusted to zero. Offset
10
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DB11 (MSB) DB10 DB1 DB0 (LSB)
LTC1272 * TA08
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11...111 11...110 11...101
FULL-SCALE TRANSITION
FS = 5V FS 1LSB = ---- 4096 00...011 00...010 00...001 00...000 0 123 LSB LSBs LSBs FS FS - 1LSB
+
AIN, INPUT VOLTAGE (IN TERMS OF LSBs)
LT1272 * TA11
Figure 9. LTC1272 Ideal Input/Output Transfer Characteristic
error must be adjusted before full-scale error. Figure 10 shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset of the op amp driving AIN (i.e., A1 in Figure 10). For zero offset error apply 0.61mV (i.e., 1/2LBS) at VIN and adjust the op amp offset voltage until the ADC output code flickers between 0000 0000 0000 and 0000 0000 0001. For zero full-scale error apply an analog input of 4.99817V (i.e., FS - 3/2LSBs or last code transition) at VIN and adjust R1 until the ADC output code flickers between 1111 1111 1110 and 1111 1111 1111.
LTC1272
APPLICATI
0V TO 5V ANALOG INPUT VIN
S I FOR ATIO
R3 15 1 AIN
+
A1 LT1007
-
LTC1272 R1 200 R2 20k 3 *ADDITIONAL PINS OMITTED FOR CLARITY
LTC1272 * TA12
AGND
Figure 10. Unipolar 0V to 5V Operation with Gain Error Adjust
Application Hints Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1272 a printed circuit board is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the LTC1272. The analog input should be screened by AGND. A single point analog ground separate from the logic system ground should be established with an analog ground plane at pin 3 (AGND) or as close as possible to the LTC1272, as shown in Figure 11. Pin 12 (LTC1272 DGND) and all other analog grounds should be connected to this single analog ground point. No other digital grounds should be connected to this analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and
1
AIN AGND 3
ANALOG INPUT CIRCUITRY
+ -
C1
Figure 11. Power Supply Grounding Practice
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the foil width for these tracks should be as wide as possible. Noise: Input signal leads to AIN and signal return leads from AGND (pin 3) should be kept as short as possible to minimize input noise coupling. In applications where this is not possible, a shielded cable between source and ADC is recommended. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible. In applications where the LTC1272 data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get LSB errors in conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a Wait state during conversion (see Slow Memory Mode interfacing), or by using three-state buffers to isolate the LTC1272 data bus. Timing and Control Conversion start and data read operations are controlled by three LTC1272 digital inputs; HBEN, CS and RD. Figure 12 shows the logic structure associated with these inputs. The three signals are internally gated so that a logic "0" is required on all three inputs to initiate a conversion. Once initiated it cannot be restarted until conversion is complete. Converter status is indicated by the BUSY output, and this is low while conversion is in progress.
LTC1272 VREF 2 C2 C3 VDD 24 C4 GROUND CONNECTION TO DIGITAL CIRCUITRY ANALOG GROUND PLANE
LTC1272 * TA13
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DIGITAL SYSTEM DGND 12
11
LTC1272
APPLICATI
S I FOR ATIO
There are two modes of operation as outlined by the timing diagrams of Figures 13 to 17. Slow Memory Mode is designed for microprocessors which can be driven into a Wait state, a Read operation brings CS and RD low which initiates a conversion and data is read when conversion is complete.
LTC1272 HBEN 19 CS 21 RD 20 5V D
D11....D0/8 ARE THE ADC DATA OUTPUT PINS DB11....DB0 ARE THE 12-BIT CONVERSION RESULTS
Figure 12. Internal Logic for Control Inputs CS, RD and HBEN
CS & RD t2 BUSY 40ns* CLK IN t14 DB11 (MSB) DB10 DB1 DB0 (LSB) t13
UNCERTAIN CONVERSION TIME FOR 30ns < t14 < 180ns *THE LTC1272 IS ALSO COMPATIBLE WITH THE AD7572 SYNCHRONIZATION MODES. SEE "DIGITAL INTERFACE" TEXT.
Figure 13. RD and CLK IN for Synchronous Operation Table 1. Data Bus Output, CS and RD = Low
PIN 4 Data Outputs* HBEN = Low HBEN = High D11 DB11 DB11 PIN 5 D10 DB10 DB10 PIN 6 D9 DB9 DB9 PIN 7 D8 DB8 DB8 PIN 8 D7 DB7 Low PIN 9 D6 DB6 Low PIN 10 D5 DB5 Low PIN 11 D4 DB4 Low PIN 13 D3/11 DB3 DB11 PIN 14 D2/10 DB2 DB10 PIN 15 D1/9 DB1 DB9 PIN 16 D0/8 DB0 DB8
Note: *D11 . . . D0/8 are the ADC data output pins DB11 . . . DB0 are the 12-bit conversion results, DB11 is the MSB
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The second is the ROM Mode which does not require microprocessor Wait states. A Read operation brings CS and RD low which initiates a conversion and reads the previous conversion result.
Q FLIP FLOP CLEAR BUSY ACTIVE HIGH ACTIVE HIGH CONVERSION START (RISING EDGE TRIGGER) ENABLE THREE-STATE OUTPUTS D11....D0/8 = DB11....DB0 ENABLE THREE-STATE OUTPUTS D11....D8 = DB11....DB8 D7....D4 = LOW D3/11....D0/8 = DB11....DB8
LTC1272 * TA14
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t CONV
LTC1272 * TA15
LTC1272
APPLICATI S I FOR ATIO
CS t1 RD t10 t2 tCONV BUSY t3 DATA t12 HOLD TRACK
LTC1272 * TA16
OLD DATA DB11-DB0
Figure 14. Slow Memory Mode, Parallel Read Timing Diagram Table 2. Slow Memory Mode, Parallel Read Data Bus Status
Data Outputs Read D11 DB11 D10 DB10 D9 DB9 D8 DB8 D7 DB7 D6 DB6 D5 DB5 D4 DB4 D3/11 DB3 D2/10 DB2 D1/9 DB1 D0/8 DB0
Data Format The output data format can be either a complete parallel load for 16-bit microprocessors or a two byte load for 8-bit microprocessors. Data is always right justified (i.e., LSB is the most right-hand bit in a 16-bit word). For a two byte read, only data outputs D7. . . D0/8 are used. Byte selection is governed by the HBEN input which controls an internal digital multiplexer. This multiplexes the 12 bits of conversion data onto the lower D7. . . D0/8 outputs (4MSBs or 8LSBs) where it can be read in two read cycles. The 4MSBs always appear on D11 . . . D8 whenever the three-state output drives are turned on. Slow Memory Mode, Parallel Read (HBEN = Low) Figure 14 and Table 2 show the timing diagram and data bus status for Slow Memory Mode, Parallel Read. CS and RD going low triggers a conversion and the LTC1272 acknowledges by taking BUSY low. Data from the previous conversion appears on the three-state data outputs. BUSY returns high at the end of conversion when the output latches have been updated and the conversion result is placed on data outputs D11 . . . D0/8.
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t5 t1 t11 t6 t7 NEW DATA DB11-DB0
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Slow Memory Mode, Two Byte Read For a two byte read, only 8 data outputs D7 . . . D0/8 are used. Conversion start procedure and data output status for the first read operation is identical to Slow Memory Mode, Parallel Read. See Figure 15 timing diagram and Table 3 data bus status. At the end of conversion the low data byte (DB7 . . . DB0) is read from the ADC. A second Read operation with HBEN high, places the high byte on data outputs D3/11 . . . D0/8 and disables conversion start. Note the 4MSBs appear on data outputs D11 . . . D8 during the two Read operations above. ROM Mode, Parallel Read (HBEN = Low) The ROM Mode avoids placing a microprocessor into a Wait state. A conversion is started with a Read operation and the 12 bits of data from the previous conversion is available on data outputs D11 . . . D0/8 (see Figure 16 and Table 4). This data may be disregarded if not required. A second Read operation reads the new data (DB11 . . . DB0) and starts another conversion. A delay at least as long as the LTC1272 conversion time plus the 1s minimum delay between conversions must be allowed between Read operations.
13
LTC1272
APPLICATI
HBEN t8 CS t1 RD t10 t2 BUSY t3 DATA t12 HOLD TRACK
LTC1272 * TA17
S I FOR ATIO
t CONV
t6 OLD DATA DB7-DB0
Figure 15. Slow Memory Mode, Two Byte Read Timing Diagram Table 3. Slow Memory Mode, Two Byte Read Data Bus Status
Data Outputs First Read Second Read D7 DB7 Low D6 DB6 Low D5 DB5 Low D4 DB4 Low D3/11 DB3 DB11 D2/10 DB2 DB10 D1/9 DB1 DB9 D0/8 DB0 DB8
CS t1 RD t11 t2 BUSY t3 DATA OLD DATA DB11-DB0 t12 HOLD TRACK
LTC1272 * TA18
t4
Figure 16. ROM Mode, Parallel Read Timing Diagram Table 4. ROM Mode, Parallel Read Data Bus Status
Data Outputs First Read (Old Data) Second Read D11 DB11 DB11 D10 DB10 DB10 D9 DB9 DB9 D8 DB8 DB8 D7 DB7 DB7 D6 DB6 DB6 D5 DB5 DB5 D4 DB4 DB4 D3/11 DB3 DB3 D2/10 DB2 DB2 D1/9 DB1 DB1 D0/8 DB0 DB0
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t9 t8 t9 t5 t1 t4 t5 t10 t11 t7 NEW DATA DB7-DB0 t3 NEW DATA DB11-DB8 t12 t7
t5 t1 t4 t5 t CONV t2 t CONV t7 t3 NEW DATA DB11-DB0 t12 t7
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LTC1272
APPLICATI
HBEN
S I FOR ATIO
t8 t9
CS t1 RD t10 t2 BUSY t3 DATA OLD DATA DB7-DB0 t12 HOLD TRACK
LTC1272 * TA19
t4
t5
tCONV
t7
Figure 17. ROM Mode, Two Byte Read Timing Diagram Table 5. ROM Mode, Two Byte Read Data Bus Status
Data Outputs First Read Second Read Third Read D7 DB7 Low DB7 D6 DB6 Low DB6 D5 DB5 Low DB5 D4 DB4 Low DB4 D3/11 DB3 DB11 DB3 D2/10 DB2 DB10 DB2 D1/9 DB1 DB9 DB1 D0/8 DB0 DB8 DB0
ROM Mode, Two Byte READ As previously mentioned for a two byte read, only data outputs D7 . . . D0/8 are used. Conversion is started in the normal way with a Read operation and the data output status is the same as the ROM Mode, Parallel Read. See Figure 17 timing diagram and Table 5 data bus status. Two more Read operations are required to access the new conversion result. A delay equal to the LTC1272 conversion time must be allowed between conversion start and the second data Read operation. The second Read operation, with HBEN high, disables conversion start and places the high byte (4 MSBs) on data outputs D3/11 . . . DO18. A third read operation accesses the low data byte (DB7 . . . DB0) and starts another conversion. The 4 MSB's appear on data outputs D11 . . . D8 during all three read operations above.
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t8 t9 t8 t9 t1 t4 t5 t1 t4 t5 t11 t2 t3 NEW DATA DB11-DB8 t7 t3 NEW DATA DB7-DB0 t12 t7
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Microprocessor Interfacing The LTC1272 is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. The HBEN input serves as a data byte select for 8-bit processors and is normally connected to the microprocessor address bus. MC68000 Microprocessor Figure 18 shows a typical interface for the MC68000. The LTC1272 is operating in the Slow Memory Mode. Assuming the LTC1272 is located at address C000, then the following single 16-bit Move instruction both starts a conversion and reads the conversion result: Move.W $C000,D0
15
LTC1272
APPLICATI
A23 A1
S I FOR ATIO
ADDRESS BUS
AS MC68000 DTACK R/W D11 D0
EN
ADDRESS DECODE LTC1272 CS BUSY RD
DATA BUS
D11 D0/8 HBEN
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1272 * TA20
Figure 18. LTC1272 MC68000 Interface
At the beginning of the instruction cycle when the ADC address is selected, BUSY and CS assert DTACK, so that the MC68000 is forced into a Wait state. At the end of conversion BUSY returns high and the conversion result is placed in the D0 register of the microprocessor. 8085A, Z80 Microprocessor Figure 19 shows a LTC1272 interface for the Z80 and 8085A. The LTC1272 is operating in the Slow Memory Mode and a two byte read is required. Not shown in the figure is the 8-bit latch required to demultiplex the 8085A common address/data bus. A0 is used to assert HBEN, so that an even address (HBEN = LOW) to the LTC1272 will start a conversion and read the low data byte. An odd address (HBEN = HIGH) will read the high data byte. This
A15 A0
ADDRESS BUS
A0
MREQ Z80 8085A WAIT RD D7 D0
EN
ADDRESS DECODE
HBEN CS BUSY LTC1272 RD
DATA BUS
D7 D0/8
LINEAR CIRCUITRY OMITTED FOR CLARITY
LTC1272 * TA21
Figure 19. LTC1272 8085A/Z80 Interface
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is accomplished with the single 16-bit Load instruction below. For the 8085A For the Z80 LHLD (B000) LDHL, (B000) This is a two byte read instruction which loads the ADC data (address B000) into the HL register pair. During the first read operation, BUSY forces the microprocessor to Wait for the LTC1272 conversion. No Wait states are inserted during the second read operation when the microprocessor is reading the high data byte. TMS32010 Microcomputer Figure 20 shows an LTC1272 TMS32010 interface. The LTC1272 is operating in the ROM Mode. The interface is designed for a maximum TMS32010 clock frequency of 18MHz but will typically work over the full TMS32010 clock frequency range. The LTC1272 is mapped at a port address. The following I/O instruction starts a conversion and reads the previous conversion result into data memory. IN A,PA (PA = PORT ADDRESS) When conversion is complete, a second I/O instruction reads the up-to-date data into memory and starts another conversion. A delay at least as long as the ADC conversion time must be allowed between I/O instructions.
PA2 PA0 PORT ADDRESS BUS DEN TMS32010 CS EN ADDRESS DECODE LTC1272 RD D11 D0 DATA BUS D11 D0/8 HBEN LINEAR CIRCUITRY OMITTED FOR CLARITY
LTC1272 * TA22
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Figure 20. LTC1272 TMS32010 Interface
LTC1272
APPLICATI S I FOR ATIO U
minimum time between conversions must be provided to allow the sample-and-hold to reacquire the analog input. Figure 22 shows that if the clock is synchronous with CS and RD, it is only necessary to short out the 10 series resistor and reverse the polarity of the 10F bypass capacitor on the VREF pin. The -15V supply is not required and can be removed, or, because there is no internal connection to pin 23, it can remain unmodified. The clock can be considered synchronous with CS and RD in cases where the LTC1272 CLK IN signal is derived from the same clock as the microprocessor reading the LTC1272.
5V VDD NC BUSY CS RD HBEN CLK OUT CLK IN D0/8 D1/9 D2/10 D3/11 * FOR GROUNDING AND BYPASSING HINTS SEE FIGURE 11 AND APPLICATION HINTS SECTION
LTC1272 * TA03
Compatibility with the AD7572 Figure 21 shows the simple, single 5V configuration recommended for new designs with the LTC1272. If an AD7572 replacement or upgrade is desired, the LTC1272 can be plugged into an AD7572 socket with minor modifications. It can be used as a replacement or to upgrade with sample-and-hold, single supply operation and reduced power consumption. The LTC1272, while consuming less power overall than the AD7572, draws more current from the 5V supply (it draws no power from the -15V supply). Also, a 1s
2.42V VREF OUTPUT
ANALOG INPUT (0V TO 5V)
+
0.1F 10F
8 OR 12-BIT PARALLEL BUS
*
Figure 21. Single 5V Supply, 3s, 12-Bit Sampling ADC
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LTC1272 A IN VREF AGND D11 (MSB) D10 D9 D8 D7 D6 D5 D4 DGND
10 F
+
0.1 F*
P CONTROL LINES
17
LTC1272
APPLICATI S I FOR ATIO U
-15V 0.1 F
2.42V* VREF OUTPUT
ANALOG INPUT (0V TO 5V)
10 *
+
10F 0.1F
D11 (MSB) D10 D9 D8 D7 P DATA BUS D6 D5 D4 DGND
CS RD HBEN
P CONTROL LINES
CLK OUT CLK IN** D0/8 D1/9 D2/10 D3/11 * THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V REFERENCE OUTPUT AS OPPOSED TO THE -5.25V OF THE AD7572. FOR PROPER OPERATION, REVERSE THE REFERENCE CAPACITOR POLARITY AND SHORT OUT THE 10 RESISTOR. ** THE ADC CLOCK SHOULD BE SYNCHRONIZED TO THE CONVERSION START SIGNALS (CS, RD) OR 1-2 LSBs OF OUTPUT CODE NOISE MAY OCCUR. DERIVING THE ADC CLOCK FROM THE P CLOCK IS ADEQUATE. | THE LTC1272 CAN ACCOMMODATE THE -15V SUPPLY OF THE AD7572 BUT DOES NOT REQUIRE IT. PIN 23 OF THE LTC1272 IS NOT INTERNALLY CONNECTED.
LTC1272 * TA04
Figure 22. Plugging the LTC1272 into an AD7572 Socket Case 1: Clock Synchronous with CS and RD
If the clock signal for the AD7572 is derived from a separate crystal or other signal which is not synchronous with the microprocessor clock, then the signals need to be synchronized for the LTC1272 to achieve best analog performance (see Clock and Control Synchronization). The best way to synchronize these signals is to drive the CLK IN pin of the LTC1272 with a derivative of the processor clock, as mentioned above and shown in Figure 22. Another way, shown in Figure 23, is to use a flip-flop to synchronize the RD to the LTC1272 with the CLK IN signal. This method will work but has two disavantages
over the first: because the RD is delayed by the flip-flop, the actual conversion start and the enabling of the LTC1272's BUSY and data outputs can take up to one CLK IN cycle to respond to a RD convert command from the processor. The sampling of the analog input no longer occurs at the processor's falling RD edge but may be delayed as much as one CLK IN cycle. Although the LTC1272 will still exhibit excellent DC performance, the flip-flop will introduce jitter into the sampling which may reduce the usefulness of this method for AC systems.
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+
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A IN VREF
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LTC1272 VDD NC| BUSY 0.1 F 10 F
+
5V 10 F
AGND
LTC1272
APPLICATI
S I FOR ATIO
LTC1272 2.42V* VREF OUTPUT 10* A IN VREF 10F 0.1F AGND D11 (MSB) D10 D9 D8 D7 P DATA BUS D6 D5 D4 DGND VDD NC| BUSY CS RD HBEN CLK OUT CLK IN D0/8 D1/9 D2/10 D3/11 EXTERNAL ASYNCHRONOUS CLOCK Q S
+
1/2 D** 74HC74 CLK
OR
* THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V REFERENCE OUTPUT AS OPPOSED TO THE -5.25V OF THE AD7572. FOR PROPER OPERATION, REVERSE THE REFERENCE CAPACITOR POLARITY AND SHORT OUT THE 10 RESISTOR. ** THE D FLIP-FLOP SYNCHRONIZES THE CONVERSION START SIGNAL (RD ) TO THE ADC CLKOUT SIGNAL TO PREVENT OUTPUT CODE NOISE WHICH OCCURS WITH AN ASYNCHRONOUS CLOCK. | THE LTC1272 CAN ACCOMMODATE THE -15V SUPPLY OF THE AD7572 BUT DOES NOT REQUIRE IT. PIN 23 OF THE LTC1272 IS NOT INTERNALLY CONNECTED.
LTC1272 * TA05
Figure 23. Plugging the LTC1272 into an AD7572 Socket Case 2: Clock Not Synchronous with CS and RD
(c)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
+
ANALOG INPUT (0V TO 5V)
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-15V 0.1 F 10 F 0.1 F
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+
5V 10 F
74HC04 RD
P CONTROL LINES
(c)
19
LTC1272
PACKAGE DESCRIPTIO
0.260 0.010* (6.604 0.254)
0.300 - 0.325 (7.620 - 8.255)
0.130 0.005 (3.302 0.127)
0.015 (0.381) MIN 0.009 - 0.015 (0.229 - 0.381)
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
0.125 (3.175) MIN
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTURSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).
0.005 (0.127) RAD MIN
0.291 - 0.299 (7.391 - 7.595) (NOTE 2) 0.010 - 0.029 x 45 (0.254 - 0.737)
0.009 - 0.013 (0.229 - 0.330)
NOTE 1 0.016 - 0.050 (0.406 - 1.270)
NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. 2. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
U
Dimensions in inches (millimeters) unless otherwise noted. N Package 24-Lead Plastic DIP
1.265* (32.131) 24 23 22 21 20 19 18 17 16 15 14 13
1
2
3
4
5
6
7
8
9
10
11
12
0.045 - 0.065 (1.143 - 1.651)
0.065 (1.651) TYP
0.050 - 0.085 (1.27 - 2.159) 0.100 0.010 (2.540 0.254)
0.018 0.003 (0.457 0.076)
N24 0594
SO Package 24-Lead Plastic SOL
0.598 - 0.614 (15.190 - 15.600) (NOTE 2) 20 19 18 17 16
24
23
22
21
15
14
13
NOTE 1
0.394 - 0.419 (10.007 - 10.643)
1 0.093 - 0.104 (2.362 - 2.642)
2
3
4
5
6
7
8
9
10
11
12 0.037 - 0.045 (0.940 - 1.143)
0 - 8 TYP
0.050 (1.270) TYP
0.004 - 0.012 (0.102 - 0.305)
0.014 - 0.019 (0.356 - 0.482)
SOL24 0392
LT/GP 0694 5K REV A * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1994

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